Current DPCH Offset
Current DPCH Offset
reports the DPCH Frame Offset (tau
DPCH
) currently in use by the test set (for the current operating mode).
DPCH Frame Offset is the offset of the DL DPCH to the P-CCPCH (see 3GPP TS 25.331 s10.3.6.21 and 25.211 Figure 29). 3GPP prescribes several rules around changing DPCH Frame Offset, which can be changed using the
Default DPCH Offset
IE (which has a resolution of 512 chips) or the
DPCH Frame Offset
IE (which has a resolution of 256 chips).
Per 3GPP, during a timing re-initialized reconfiguration (Timing Indication IE = Initialise), the
Default DPCH Offset
IE and
DPCH Frame Offset
IE in the reconfiguration message must be set to the same value. This means the resolution of the timing adjustment on a timing re-initialized reconfiguration is 512 chips. See 3GPP TS 25.331 s8.3.5.1.2.
Per 3GPP, during a timing maintained reconfiguration (Timing Indication IE = Maintain), the reconfiguration message must not include a
Default DPCH Offset
IE; only the
DPCH Frame Offset
IE is signalled. However, if the UE is ordered to adjust its timing by more than 256 chips, then it will reject the reconfiguration. This means the resolution of the timing adjustment on a timing maintained reconfiguration is 256 chips, but the maximum timing change is 256 chips. See 3GPP TS 25.331 s8.2.2.3.
Per 3GPP, there is a further constraint on when DPCH Frame Offset can be changed. According to 3GPP 25.331 v5.17.0 s8.6.6.28, timing re-initialized reconfigurations are intended to be exclusively used for hard handovers (i.e. where the UE changes UARFCNs and/or all Primary Scrambling Codes for all links in the active set as part of the reconfiguration, see 3GPP TS 25.331 v5.17.0 s8.6.6.3a). 25.331 states that the UE's behavior is undefined if the network sets the Timing Indication IE to Initialise on a non-hard handover (i.e. where the UARFCNs and one or more Primary Scrambling Codes remain unchanged as part of the reconfiguration). Therefore, to change DPCH Frame Offset using the
Default DPCH Offset
IE (i.e. to a value of 0, 1, 2, 3, 4, or 5 x 512 chips), you must also change UARFCNs or Primary Scrambling Codes during the reconfiguration.
In active cell operating mode, the test set can signal the DPCH Frame Offset to the UE in one of two ways:
-
During call establishment, using the
Default DPCH Offset (DOFF)
setting: Sets DPCH Frame Offset to 0, 1, 2, 3, 4 or 5 x 512 chips during call establishment (you cannot change the
Default DPCH Offset (DOFF)
setting while on a connection, you must set it before establishing the connection).
-
While on a connection, using the following settings:
-
RBR
or
TCR Default DPCH Offset (DOFF)
: Sets DPCH Frame Offset to 0, 1, 2, 3, 4 or 5 x 512 chips while on a connection (using a Radio Bearer Reconfiguration or Transport Channel Reconfiguration, respectively). Note, 3GPP TS 25.331 v5.17.0 s8.6.6.28 states that the timing re-initialized reconfiguration required to send the
Default DPCH Offset
IE must also include a change in UARFCN or Primary Scrambling Code, or the UE's behavior is undefined. Both the Radio Bearer Reconfiguration and Transport Channel Reconfiguration can be used to change UARFCNs.
-
RBR
or
TCR Relative DPCH Frame Offset
: Changes the current DPCH Frame Offset by -256, 0 or +256 chips while on a connection (using a Radio Bearer Reconfiguration or Transport Channel Reconfiguration, respectively).
In FDD test operating mode, you can set DPCH Frame Offset to 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 x 256 chips using the
DPCH Frame Offset
setting. Note, you must then also set this DPCH Frame Offset in the UE so that it can successfully decode the test set's signal; the test set does not provide any signalling to the UE in
FDD Test Operating Mode
and thus will not signal the DPCH Frame Offset setting to the UE.
Current DPCH Offset
is not displayed on the front panel screen while in FDD test operating mode because in FDD test operating mode,
Current DPCH Offset
is always equal to the
DPCH Frame Offset
setting.
In active cell operating mode, if a DL DPCH is not active,
Current DPCH Offset
simply reflects the value of the
Default DPCH Offset (DOFF)
setting.
GPIB command:
CALL:STATus:DPCHannel:OFFSet?
Implications of the Current DPCH Offset
The UL DPCH is always transmitted 1024 chips after the DL DPCH. Thus, changing DPCH Frame Offset, which offsets the DL DPCH from the P-CCPCH, changes the offset between the UL DPCH and P-CCPCH by the same amount.
When on an HSDPA or HSPA connection
(lab application or feature licensed test application only)
, changing the DPCH Frame Offset results in a change in the offset between the UL DPCH and HS-DPCCH, because the HS-DPCCH is always transmitted 12.5 slots after the start of the HS-SCCH (which is always aligned to the P-CCPCH). In other words, changing the DPCH Frame Offset shifts the UL DPCH's position in time relative to the HS-DPCCH.
The following table indicates the time offset present between the HS-DPCCH and UL DPCH for the various DPCH Frame Offset values available in the test set.
HS-DPCCH/DPCCH Alignment vs. DPCH Frame Offset
|
DPCH Frame Offset
|
HS-DPCCH to UL DPCH Alignment |
|
0 chips = 0 x 256 chips = 0 x 512 chips
|
+0.1 slot (the HS-DPCCH slot boundary occurs
66.7 us/256 chips after the UL DPCH slot boundary)
|
|
256 chips = 1 x 256 chips
|
0.0 slot (the HS-DPCCH and UL DPCH slot boundaries
are aligned)
|
|
512 chips = 2 x 256 chips = 1 x 512 chips
|
-0.1 slot (the HS-DPCCH slot boundary occurs
66.7 us/256 chips before the UL DPCH slot boundary)
|
|
768 chips = 3 x 256 chips |
-0.2 slot (the HS-DPCCH slot boundary occurs
133.3 us/512 chips before the UL DPCH slot boundary)
|
|
1024 chips = 4 x 256 chips = 2 x 512 chips |
-0.3 slot (the HS-DPCCH slot boundary occurs
200 us/768 chips before the UL DPCH slot boundary)
|
|
1280 chips = 5 x 256 chips |
-0.4 slot (the HS-DPCCH slot boundary occurs
266.7 us/1024 chips before the UL DPCH slot boundary)
|
|
1536 chips = 6 x 256 chips = 3 x 512 chips |
-0.5 slot (the HS-DPCCH slot boundary occurs
333.3 us/1280 chips before the UL DPCH slot boundary)
|
|
1792 chips = 7 x 256 chips |
-0.6 slot (the HS-DPCCH slot boundary occurs
400 us/1536 chips before the UL DPCH slot boundary)
|
|
2048 chips = 8 x 256 chips = 4 x 512 chips |
-0.7 slot (the HS-DPCCH slot boundary occurs
466.7 us/1792 chips before the UL DPCH slot boundary)
|
|
2304 chips = 9 x 256 chips |
-0.8 slot (the HS-DPCCH slot boundary occurs
533.3 us/2048 chips before the UL DPCH slot boundary)
|
|
2560 chips = 10 x 256 chips = 5 x 512 chips |
-0.9 slot (the HS-DPCCH slot boundary occurs
600 us/2304 chips before the UL DPCH slot boundary)
|