CALL:CLPControl

Function

Sets the uplink inner loop power control to decrease power in one step (see CALL[:CELL]:CLPControl:UPLink:STEPsize ).

This function is only used when the UL CL power control is set to use alternating bits (see CALL[:CELL]:CLPControl:UPLink:MODE ).

Requirements

Test or Lab Application Revision: A.01 and above

Programming Example

 
OUTPUT 714;"CALL:CELL:CLPCONTROL:UPLINK:IMMEDIATE:DOWN"

Function

Sets the uplink inner loop power control to increase power in one step (see CALL[:CELL]:CLPControl:UPLink:STEPsize ).

This function is only used when the UL CL power control is set to use alternating bits (see CALL[:CELL]:CLPControl:UPLink:MODE ).

Requirements

Test or Lab Application Revision: A.01 and above

Programming Example

 
OUTPUT 714;"CALL:CELL:CLPCONTROL:UPLINK:IMMEDIATE:UP"

Function

Sets/queries the UL CL Power Control Mode for Active Cell Operating Mode .

Setting

Range:

• ACTive (Active bits)
• DOWN (All Down bits)
• UDOWn (Alternating bits)
• UDOWn10 (10 Up/Down bits)
• UP (All Up bits)

Query

Range: ACT|DOWN|UDOW|UDOW10|UP

*RST Setting

ACTive

Requirements

Test or Lab Application Revision: A.01 and above

Programming Example

 
OUTPUT 714;"CALL:CELL:CLPControl:UPLink:MODE ACTive"
!Sets the uplink closed loop power control to active.

Function

Sets/queries UL CL Power Ctrl Algorithm .

This setting can only be changed while the Cell Operating Mode is "Cell Off", or while the cell operating mode is "Active Cell" and the call status is IDLE. Attempting to change this setting while in any other mode will result in an error.

Setting

Range:

• ALG1
• ALG2

Query

Same as setting

*RST Setting

ALG2

Requirements

Test or Lab Application Revision: A.02 and above

Programming Example

 
OUTPUT 714;"CALL:CELL:CLPControl:UPLink:ALGorithm ALG1"
! Sets the uplink closed loop power control algorithm to 1.

Function

Sets/queries UL CL Power Ctrl Stepsize .

This setting can only be changed while the Cell Operating Mode is "Cell Off", or while the cell operating mode is "Active Cell" and the call status is IDLE. Attempting to change this setting while in any other mode will result in an error.

This setting can only be changed when CALL[:CELL]:CLPControl:UPLink:ALGorithm is set to ALG1 . Also, if CALL[:CELL]:CLPControl:UPLink:ALGorithm is set to ALG2 , this setting is returned to its default value of 1 dB .

Setting

Range: 1 to 2 dB

Resolution: 1 dB

Query

Same as setting

*RST Setting

1 dB

Requirements

Test or Lab Application Revision: A.03 and above

Programming Example

 
OUTPUT 714;"CALL:CLPControl:UPLink:STEPsize 2"
! Sets the uplink closed loop power control step size to 2 dB.