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Phase Discontinuity Measurement Description
Last updated: January 16, 2009
How is a Phase Discontinuity Measurement Made?
The Phase Discontinuity measurement can be used to measure a non-HSDPA signal (DPCH only) or an HSDPA signal (DPCH + HS-DPCCH).
To perform measurements on a non-HSDPA signal, set
Trigger Source
to
Protocol
or
External
. See
Non-HSDPA Phase Discontinuity
for additional information.
To perform measurements on an HSDPA signal (
lab application or feature-licensed test application only
), set
Trigger Source
to HS-DPCCH. See
HSDPA Phase Discontinuity
.
Non-HSDPA Phase Discontinuity
To measure phase discontinuity on a non-HSDPA signal (DPCH only), you must set
Trigger Source
to
Protocol
or
External
.
3GPP TS 34.121 s5.13.3.1 states: "
Phase discontinuity is the change in phase between any two adjacent timeslots. The EVM for each timeslot (excluding the transient periods of 25 us on either side of the nominal timeslot boundaries), shall be measured according to subclause 5.13.2. The frequency, absolute phase, absolute amplitude and chip clock timing used to minimise the error vector are chosen independently for each timeslot. The phase discontinuity result is defined as the difference between the absolute phase used to calculate EVM for the preceding timeslot, and the absolute phase used to calculate EVM for the succeeding timeslot.
"
Graphical Description of Phase Discontinuity (3GPP TS 34.121 5.13.3.1)
"
The best-fit rate of change of phase for each timeslot is calculated using the same process as used to minimize the EVM. This best-fit rate of change of phase is by definition the frequency error result for the timeslot. Due to the presence of power steps in the test, the data used for the best-fit calculation shall exclude the 25 us transition period at the beginning and end of each timeslot. The best-fit rate of change of phase for each timeslot is then extrapolated in both directions onto the timeslot boundaries. The phase discontinuity result at any one slot boundary is the difference between the extrapolated phase at the end of the timeslot preceding the slot boundary and the extrapolated phase at the start of the timeslot following the slot boundary.
"
The non-HSDPA phase discontinuity measurement in the test set measures the change in phase between adjacent slots as prescribed in the test standard. Therefore the phase discontinuity reported for any given slot is the extrapolated starting phase of that slot minus the extrapolated ending phase of the previous slot (the 25 us transient periods on either side of the slot boundaries are excluded during the best-fit calculation of the rate of change of phase, such that only 617 us of each slot is used in the best-fit calculation).
The non-HSDPA phase discontinuity measurement also returns the extrapolated starting phase of each slot (normalized to the extrapolated starting phase of the
Reference Timeslot
), the power of each slot, and several waveform quality results for each slot (see
Phase Discontinuity Measurement Results
).
The total number of slots measured when the non-HSDPA phase discontinuity measurement is initiated is determined by
Number of Pattern Repetitions
or by
Measurement Interval
, depending upon the
Power Control Pattern
setting.
HSDPA Phase Discontinuity
This section is only applicable to the lab application or feature-licensed test application.
To measure phase discontinuity on an HSDPA signal (DPCH + HS-DPCCH), you must set
Trigger Source
to
HS-DPCCH
.
3GPP 34.121 s5.13.1AA states: "
Phase discontinuity for HS-DPCCH is the change in phase due to the transmission of the HS-DPCCH. In the case where the HS-DPCCH timeslot is offset from the DPCCH timeslot, the period of evaluation of the phase discontinuity shall be the DPCCH timeslot that contains the HS-DPCCH slot boundary. The phase discontinuity for HS-DPCCH result is defined as the difference between the absolute phase used to calculate the EVM for that part of the DPCCH timeslot prior to the HS-DPCCH slot boundary, and the absolute phase used to calculate the EVM for remaining part of the DPCCH timeslot following the HS-DPCCH slot boundary. In all cases the subslot EVM is measured excluding the transient periods of 25 us. Since subslot EVM is only defined for intervals of at least one half timeslot, the phase discontinuity for HS-DPCCH is only defined for non-aligned timeslots when the offset is 0.5 slots.
"
The HSDPA phase discontinuity measurement in the test set can be used to measure the change in phase across HS-DPCCH boundaries as prescribed in the test standard.
You can specify whether 0.5 slot or 1.0 slot steps are evaluated by the measurement using the
HS-DPCCH Measurement Step Interval
setting. You can change the placement of the measurement trigger (which coincides with step 1) using the
HS-DPCCH Trigger Subframe Alignment
,
HS-DPCCH Trigger Slot Alignment
and
HS-DPCCH Trigger Subslot Alignment
settings.
Measurement Step Interval and Trigger Placement for HSDPA
The phase discontinuity reported for any given step is the extrapolated starting phase of that step minus the extrapolated ending phase of the previous step (the 25 us transient periods on either side of the step are excluded during the best-fit calculation of the rate of change of phase, such that only 283 us or 617 us is used in the best-fit calculation depending upon whether
HS-DPCCH Measurement Step Interval
is set to
0.5 slot
or
1.0 slot
, respectively).
The HSDPA phase discontinuity measurement also returns the extrapolated starting phase of each step (normalized to the extrapolated starting phase of step 0), the power of each step, and several waveform quality results for each step (see
Phase Discontinuity Measurement Results
).
The total number of steps measured when the measurement is initiated is determined by
HS-DPCCH Measurement Step Count
setting.
When
Trigger Source
is set to
HS-DPCCH
, when the measurement is initiated the test set checks to see that
UL CL Power Ctrl Algorithm
is set to
Two
and
UL CL Power Ctrl Stepsize
is set to
1 dB
. If not, the test set sends the UE a Physical Channel Reconfiguration message with these values. (When the measurement completes, the values are returned to their pre-measurement states.) The test set then transmits alternating power control bits throughout the duration of the measurement.
Operating Mode Considerations
The phase discontinuity measurement is supported in
Active Cell Operating Mode
and
FDD Test Operating Mode
.
In
Active Cell Operating Mode
, you must be on a call before running the phase discontinuity measurement. You must set the UE to the proper power level before running the measurement by setting
UL CL Power Control Mode
to
Active Bits
and
UE Target Power
to the desired level.
In
FDD Test Operating Mode
, you must ensure that the UE is synchronized to the downlink frame clock before running the measurement. You must properly range the test set's receiver before running the measurement by setting the
Expected Power
and the UE's output power level accordingly. It is recommended that you set
Power Control
to
Auto
and use the
UE Target Power
setting to set the expected power (rather than setting
Power Control
to
Manual
and using the
Manual Power
setting). Auto power control is recommended because after completion of the measurement, the test set sets
UE Target Power
to the power level of the last measured step to aid in maintaining the connection between the test set and UE. The test set does not change the
Manual Power
setting to match the power level of the last measured step.
Phase Discontinuity Measurement Parameters
Non-HSDPA Phase Discontinuity Measurement Parameters
The following settings are only applicable when
Trigger Source
is set to
Protocol
or
External
.
-
Power Control Pattern
When
Power Control Pattern
is set to
5UP/4DOWN
or
5DOWN/4UP
:
-
When the measurement is initiated, the test set checks to see that
UL CL Power Ctrl Algorithm
is set to
One
and
UL CL Power Ctrl Stepsize
is set to
1 dB
. If not, the test set sends the UE a Physical Channel Reconfiguration message with these values. (When the measurement completes, the values are returned to their pre-measurement states.)
-
The test set then sends a repeating pattern of 5 up bits then 4 down bits or 5 down bits then 4 up bits, until the
Number of Pattern Repetitions
is reached. Thus the total number of slots measured by the test set is determined by the
Number or Pattern Repetitions
setting.
-
The
Reference Timeslot
(first timeslot measured) is always slot 14 of the frame prior to the start of the power control pattern.
-
When the measurement completes, in an attempt to maintain the connection with the UE the test set sets
UE Target Power
to the UE's output power in the final measured slot and sets
UL CL Power Control Mode
to
Active Bits
when in
Active Cell Operating Mode
or to
Alternating Bits
when in
FDD Test Operating Mode
.
When
Power Control Pattern
is set to
NONE
:
-
The power control pattern sent to the UE when the measurement is initiated is determined by the
UL CL Power Control Mode
setting (for example,
10 Up/Down bits
).
-
The total number of slots measured by the test set is determined by the
Measurement Interval
setting.
-
The
Reference Timeslot
(first timeslot measured) is determined by the
Reference Timeslot
setting.
When
Power Control Pattern
is set to
18 UP
or
18 DOWN
:
-
When the measurement is initiated, the test set checks to see that
UL CL Power Ctrl Algorithm
is set to
One
and
UL CL Power Ctrl Stepsize
is set to
1 dB
. If not, the test set sends the UE a Physical Channel Reconfiguration message with these values. (When the measurement completes, the values are returned to their pre-measurement states.)
-
The test set then sends 18 up bits or 18 down bits. When
Power Control Pattern
is set to
18 UP
or
18 DOWN
, the
Number of Pattern Repetitions
is fixed to 1. Thus, the total number of slots measured by the test set for one measurement execution is 19 (the
Reference Timeslot
plus 18 slots).
-
To measure phase discontinuity across the entire dynamic range of your UE, repeatedly execute the phase discontinuity measurement until the desired range has been tested. Each time the measurement completes, the test set sets
UE Target Power
to the UE's output power in the final measured slot. Thus, there is no need to change the
UE Target Power
between measurements that are intended to span the dynamic range of the UE, unless you choose to include some overlap between the consecutive measurements.
-
The
Reference Timeslot
(first timeslot measured) is always slot 14 of the frame prior to the start of the power control pattern.
-
Number of Pattern Repetitions
When
Power Control Pattern
is set to
5UP/4DOWN
or
5DOWN/4UP
, the
Number of Pattern Repetitions
setting determines the number of times the chosen pattern is sent to the UE. The measurement ends once the specified number of pattern repetitions has been sent, so this setting determines the total number of slots measured by the test set. The total number of timeslots measured is equal to the
Reference Timeslot
plus 9*(
Number of Pattern Repetitions
). The maximum number of timeslots that can be measured is thus 91.
When
Power Control Pattern
is set to
NONE
, this setting is ignored.
When
Power Control Pattern
is set to
18 UP
or
18 DOWN
, this setting is fixed to
1
.
-
Reference Timeslot
When
Power Control Pattern
is set to
NONE
, the
Reference Timeslot
setting determines the first timeslot to be measured (within the first available frame after the measurement is initiated). For example, if you set
Reference Timeslot
to
4
, then the first slot measured will be the 5th slot of the frame (because the slots are numbered 0 to 14 in a frame).
When
Power Control Pattern
is set to
5UP/4DOWN
,
5DOWN/4UP
,
18 UP
or
18 DOWN
, the
Reference Timeslot
is always slot 14 of the frame prior to the start of the power control pattern. Thus, this setting is ignored.
The test set compares all other slots to the
Reference Timeslot
when determining the
Phase (in degrees)
result.
-
Measurement Interval
When
Power Control Pattern
is set to
NONE
the
Measurement Interval
setting determines the number of adjacent slots for the test set to measure. The test set measures the number of slots specified by the
Measurement Interval
setting, starting with the timeslot specified by
Reference Timeslot
.
When
Power Control Pattern
is set to
5UP/4DOWN
,
5DOWN/4UP
,
18 UP
or
18 DOWN
, this setting is ignored.
HSDPA Phase Discontinuity Measurement Parameters
This section is only applicable to the lab application or feature-licensed test application.
The following settings are only applicable when
Trigger Source
is set to
HS-DPCCH
.
Phase Discontinuity Measurement Results
The following results are available via the
FETCh:WPDiscon[:ALL]?
command, or from the front panel (see
How Do I Make a Phase Discontinuity Measurement?
).
The following results are only available via the
FETCh:WPDiscon:EVM:PEAK:WORSt?
GPIB command (not from the front panel).
-
Worst Case Peak EVM Step Number:
Indicates which of the measured steps had the worst peak EVM. The first measured step is numbered 0. Thus, for example, if the reported
Worst Case Peak EVM Step Number
is
90
, the 91st step measured had the worst peak EVM result.
-
Worst Case Peak EVM (in % peak):
Provides the peak EVM result for the measured step with the worst peak EVM.
Results Returned for Each Step Measured:
As mentioned above, the measurement indicates which step(s) had the worst measurement results. The measurement also returns all measurement results for all measured steps.
The measurement results for all steps are available from the front panel (except peak EVM; peak EVM is only available via GPIB). See
How Do I Make a Phase Discontinuity Measurement?
.
You can also query all of the measurement results (except peak EVM) for a particular step using the
FETCh:WPDiscon:STEP?<sp><step num>
command. To query the peak EVM for a particular step, use the
FETCh:WPDiscon:EVM:PEAK:STEP?<sp><step num>
command.
You can also query a particular measurement result for all steps using the
FETCh:WPDiscon:TRACe?<sp>DISC|PHASE|POW|EVM|PERR|FERR|MERR|TERR|OOFF|EVMPK
command. Simply append the command with the specific measurement result you are interested in, and the results for all measured steps are returned.
-
Phase Discontinuity (in degrees)
The phase discontinuity reported for any given step is the extrapolated starting phase of that step minus the extrapolated ending phase of the previous step. Thus, no phase discontinuity is reported for the first step (the
Reference Timeslot
for non-HSDPA phase discontinuity).
-
Phase (in degrees)
The phase reported for any given step is the extrapolated starting phase of that step normalized to the extrapolated starting phase of the first step (the
Reference Timeslot
for non-HSDPA phase discontinuity). Thus, the phase of the first step is always zero.
-
Power (in dBm)
The average power is reported for each step (this is a channel power measurement over the step, excluding the transient periods of 25 us on either side of the nominal step boundaries, with the RRC filter off).
-
rms EVM (in % rms)
-
Phase Error (in degrees)
-
Frequency Error (in Hz)
-
Magnitude Error (in %)
-
Time Error (in chips)
-
Origin Offset (in dB)
-
Peak EVM (in % peak)
Key 3GPP Tests Performed Using the Phase Discontinuity Measurement
The phase discontinuity measurement can be used to test 3GPP TS 34.121 5.13.1AA, 5.13.3, as well as the 3GPP TS 25.101 6.8.4.1 minimum requirement:
Phase Discontinuity Minimum Requirement
|
Phase Discontinuity (in degrees) |
Maximum Allowed Rate of Occurrence (in Hz) |
|
Phase Discontinuity </= 30 |
1500 |
|
30 < Phase Discontinuity </= 60 |
300 |
|
Phase Discontinuity > 60 |
0 |
Regarding 3GPP TS 34.121 test 5.13.3: section 5.13.3.4.2 specifies
"NOTE: In order to make it practical to measure the entire power control dynamic range (between min power threshold and max power threshold with suitable margins), it is permissible to segment the power control sequences into smaller subsequences. Except when within 5 dB of the upper or lower thresholds, segmentation will require sufficient overlap such that every power step in one direction is followed by four steps in the other direction."
This overlap ensures that the full dynamic range of the UE is tested, as there is some uncertainty in the actual UE output power based on
Active Bits
closed loop power control. Without overlapping the subsequence ending and starting powers, some portion of the UE's output power range may not be tested. To implement the specified overlap, after running the
Phase Discontinuity
measurement with
Power Control Pattern
set to
5UP/4DOWN (
or
5DOWN/4UP
), instead of immediately running the measurement again to test the next subsequence, first set
UE Target Power
to 4 dB below (or above) the ending power of the prior test subsequence. A faster method of ensuring that the full dynamic range of the UE is tested is as follows: after testing two subsequences, compare the
Power (in dBm)
of the first slot in the current subsequence with the power of the last slot in the prior subsequence to ensure that they are equal or have some overlap. If not, set
UE Target Power
accordingly and retest the subsequence.
Phase Discontinuity Measurement Input Signal Requirements
-
This measurement does not autorange, therefore the expected power level from the mobile station (UE) is set using the current UE Target Power setting, or by using manual receiver power control and specifying the expected power level. See
Receiver Control
.
-
Frequency: 800 to 1000 MHz, 1700 to 1990 MHz
-
Input level:
-
-25 dBm to +28 dBm (other measurements returned with Phase Discontinuity)
-
-61 dBm to +28 dBm (Phase Discontinuity measurement only)
-
Maximum measurable EVM: 35% (measurement is only specified for EVM <17.5%)
-
Maximum measurable frequency error: +/- 1 kHz
-
Maximum measurable timing error: +/- 10 us
Phase Discontinuity Measurement Calibration
You must calibrate the phase discontinuity measurement using the measurement calibration procedure (see
Calibrating the Test Set
).
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