Port Configuration

LVDS

sets the logic type for the N5102A module to low voltage differential signaling (LVDS) as the logic data type.

LVTTL

sets the logic type for the N5102A module to a low voltage TTL signal as the logic data type.

CMOS33

sets a 3.3 volt CMOS signal as the logic data type.

CMOS25

sets a 2.5 volt CMOS signal as the logic data type.

CMOS18

sets a 1.8 volt CMOS signal as the logic data type.

CMOS15

sets a 1.5 volt CMOS signal as the logic data type.

Changing the logic type changes the voltage levels. To avoid potential damage to your DUT or the N5102A module, first verify that the new logic type and voltage are appropriate.

IQ to IQ

Samples are transmitted as 16 bits of ’r;I’ followed by 16 bits of ’r;Q’ ; a complete sample is 32 bits or 4 bytes. At the device interface, the 16 bits of ’r;I’ are on the 16 ’r;I’ parallel lines; the 16 bits of ’r;Q’ are on the 16 ’r;Q’ parallel lines. Both I and Q are transmitted in one clock cycle. 

IQ to Interleaved QI

Samples are transmitted as 16 bits of 'I’ followed by 16 bits of 'Q’; a complete sample is 32 bits or 4 bytes. At the device interface, the 16 bits of 'I’ and the 16 bits of 'Q’ are both on the 16 'I’ parallel lines. The 'I’ and 'Q’ bits are interleaved, with the 'Q’ bits coinciding with the rising edge of the clock, and the 'I’ bits occurring with the falling edge of the clock. The 'Q’ bits for a given sample precede the 'I’ bits for that sample.  

IQ to Interleaved IQ

Samples are transmitted as 16 bits of 'I’ followed by 16 bits of 'Q’; a complete sample is 32 bits or 4 bytes. At the device interface, the 16 bits of 'I’ and the 16 bits of 'Q’ are both on the 16 'I’ parallel lines. The 'I’ and 'Q’ bits are interleaved, with the 'I’ bits coinciding with the rising edge of the clock, and the 'Q’ bits occurring with the falling edge of the clock. The 'I’ bits for a given sample precede the 'Q’ bits for that sample.   

IQ to IQ

Samples are transmitted as 16 bits of ’r;I’ followed by 16 bits of ’r;Q’; a complete sample is 32 bits or 4 bytes. At the device interface, the 16 ’r;I’ bits of a sample appear as a serial stream on the I0 line. The 16 ’r;Q’bits of a sample appear on the I1 line. Accompanying these two data lines are separate lines for clock and frame signals. The frame signal goes high for one clock cycle during I0 and Q0; for the rest of the sample, the frame is low.  

IQ to Sample Interleaved IQ

Samples are transmitted as 16 bits of ’r;I’ followed by 16 bits of ’r;Q’; a complete sample is 32 bits or 4 bytes. At the device interface, the 16 ’r;I’ bits as well as the 16 ’r;Q’ bits of a sample appear as a single serial stream on the I0 line. The ’r;I’ bits of a given sample precede the associated 16 ’r;Q’ bits. The frame signal goes high for one clock cycle during the first ’r;I’ bit of a sample; for the rest of the sample, the frame signal is low.  

IQ to Bit Interleaved IQ

Samples are transmitted as 16 bits of ’r;I’ followed by 16 bits of ’r;Q’; a complete sample is 32 bits or 4 bytes. At the device interface, the 16 ’r;I’ bits as well as the 16 ’r;Q’ bits of a sample appear as a single serial stream on the I0 line, with each ’r;I’ bit preceding the associated ’r;Q’ bit. The frame signal goes high for one clock cycle during the first ’r;I’ bit of a sample; during the rest of the sample, the frame signal is low.

Positive

The frame marker is set high during the first data sample.

Negative

The frame marker is set low during the first data sample.