Channel Power Measurement Description

Channel Power Measurement Description

Last updated: November 10, 2006

How is a Channel Power Measurement Made?

Channel power measurements are made by analyzing a digitized version of the input signal's downconverted IF using the test set's DSP (see Block Diagram ). The measurement triggers on the test set's internal ~1.667 ms slot clock. The measurement thus always starts at the beginning of a slot. Depending upon the Measurement Speed setting, the test set either measures the power over an entire slot or just the first 1/4 of the slot, and reports the average power. Because the measurement is triggered on the slot clock rather than the frame clock, any slot within the frame can be measured, increasing measurement speed. The measurement only measures power within a 1.23 MHz measurement bandwidth. The measurement is cross-calibrated with digital average power to determine the absolute power level. The result is given in dBm/1.23 MHz.

Channel Power Measurement Parameters

Channel Power Measurement Results

An example measurement result display (for subtype 0 physical layer) is shown below:

An example measurement result display (for subtype 2physical layer) is shown below:

Channel Power Input Signal Requirements

Input Signal Requirements

Key C.S0033 Tests Performed using the Channel Power Measurement

4.3.5 Minimum Controlled Output Power

Calibrating the Channel Power Measurement

Refer to Calibrating the Test Set for a description of channel power calibration.

Related Topics


Manual Operation: Measuring Channel Power

Programming a Channel Power Measurement

Channel Power Measurement Troubleshooting

Test Adherence to Standards

C.S0029 Test Application Specification Description (TAP/ETAP)